The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed inter-layer dielectrics and interconnected metallization layers defining conductive patterns An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different metallization layers, i.e., upper and lower metallization layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via opening is typically formed by depositing an inter-layer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening in the inter-layer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interdielectic layer is removed by chemical-mechanical polishing (CW). One such method is known as damascene and basically involves forming an opening and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via opening section in communication with an upper trench opening section, and filling the opening with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and the distance between interconnects decreases, the RC delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.18 micron and below, e.g., about 0.15 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a replacement material for aluminum (Al) in ultra large scale interconnection metalizations. Cu is relatively inexpensive, easy to process, has a lower resistivity than Al, and has improved electrical properties vis-a-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CNO, as in Teong, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through the interdielectic layer, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW), and silicon nitride (Si.sub.3 N.sub.4) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the interdielectric layer, but includes interfaces with other metals as well.
In forming Cu and/or Cu alloy interconnects, as by damascene metallization techniques, Cu will be exposed in the bonding pad area located on the top surface of the integrated circuit structure or uppermost metallization layer. The bonding pad area is the region where wires make contact with bonding pads to form electrical connection with the interconnects. In this case, where the Cu and/or Cu alloy interconnects are exposed in the bonding pad area, it is designed to be used as an interconnect and as a bonding pad.
Conventional techniques for wire bonding, however, are not compatible with bonding pads comprising Cu or a Cu alloy. Conventional technology employs bonding techniques, such as wedge bonding and ultrasonic bonding, etc., which require thermal agitation, i.e., rubbing the wire against the bonding pad to form a bond therebetween. Such conventional technology is suitable for bonding either gold(Au), Au alloy, Al or Al alloy wires to aluminum pads. However such conventional techniques are not suitable for bonding to Cu pads, since Cu is easily oxidized, form insulator.
In U.S. Pat. No. 5,785,236 issued to Cheung et al., methodology is disclosed for electrically connecting wires to a Cu interconnect by forming an intermediate Al pad on the Cu interconnect and bonding the wires to the Al pad. However, inter-diffusion of Cu and Al occurs between the Cu interconnect and the Al pad, thereby disadvantageously increasing the resistance of the interconnection system.
There exists a need for a reliable wire bonded Cu or Cu alloy interconnect structure. There also exists a need for methodology enabling wire bonding to a Cu or Cu alloy interconnect via an Al pad without Cu and Al inter-diffusion.